/*-----------------------------------------------------------
  UX1200E register define file		Ver.1.00

  Copyright (c) 2006- Shimafuji Electric Inc.
  2006/10/5
 -----------------------------------------------------------*/
#ifndef __UX1200E_H__

// UART1
#define	UART_1RBR		0xB8800C00
#define	UART_1THR		0xB8800C00
#define	UART_1DLL		0xB8800C00
#define	UART_1IER		0xB8800C02
#define	UART_1DLM		0xB8800C02
#define UART_1FCR		0xB8800C04
#define	UART_1LCR		0xB8800C06
#define	UART_1LSR		0xB8800C0A
#define	UART_1RESET		0xB8800C10

// UART2
#define	UART_2RBR		0xB8800C40
#define	UART_2THR		0xB8800C40
#define	UART_2DLL		0xB8800C40
#define	UART_2IER		0xB8800C42
#define	UART_2DLM		0xB8800C42
#define UART_2FCR		0xB8800C44
#define	UART_2LCR		0xB8800C46
#define	UART_2LSR		0xB8800C4A
#define	UART_2RESET		0xB8800C50

// CSI
#define	CSI_MODEREG		0xB8800C80
#define	CSI_CLKSELREG		0xB8800C81
#define	CSI_SIRBREG		0xB8800C82
#define	CSI_SOTBREG		0xB8800C84
#define	CSI_SIRBEREG		0xB8800C86
#define	CSI_SOTBFREG		0xB8800C88
#define	CSI_SIOREG		0xB8800C8A
#define	CSI_CNTREG		0xB8800C90
#define	CSI_INTREG		0xB8800C92
#define	CSI_IFIFOVREG		0xB8800C94
#define	CSI_OFIFOVREG		0xB8800C96
#define	CSI_IFIFOREG		0xB8800C98
#define	CSI_OFIFOREG		0xB8800C9A
#define	CSI_FIFOTRGREG		0xB8800C9C

// INTC
#define	INTC_CH1_LEVEL		0xB8800B00
#define	INTC_CH2_LEVEL		0xB8800B02
#define	INTC_CH3_LEVEL		0xB8800B04
#define	INTC_CH4_LEVEL		0xB8800B06
#define	INTC_CH5_LEVEL		0xB8800B08
#define	INTC_CH6_LEVEL		0xB8800B0A
#define	INTC_CH7_LEVEL		0xB8800B0C
#define	INTC_CH8_LEVEL		0xB8800B0E
#define	INTC_CH9_LEVEL		0xB8800B10
#define	INTC_CH10_LEVEL		0xB8800B12
#define	INTC_CH11_LEVEL		0xB8800B14
#define	INTC_CH12_LEVEL		0xB8800B16
#define	INTC_CH13_LEVEL		0xB8800B18
#define	INTC_CH14_LEVEL		0xB8800B1A
#define	INTC_CH15_LEVEL		0xB8800B1C
#define	INTC_CH16_LEVEL		0xB8800B1E
#define	INTC_INT_CLR		0xB8800B20
#define	INTC_INT_SET		0xB8800B22
#define	INTC_INT_PENDING	0xB8800B24
#define	INTC_LEVEL_EDGE		0xB8800B26
#define	INTC_INT_MASK		0xB8800B28
#define	INTC_LEVEL_MASK		0xB8800B2A
#define	INTC_INT_ACK		0xB8800B2C
#define	INTC_INT_VECTOR		0xB8800B2E
#define	INTC_INT_STATUS		0xB8800B30
#define	INTC_INT_ACT_LV		0xB8800B32

// GPIO
#define	GPIO_SEL		0xB8800900
#define	GPIO_IOSEL1		0xB8800910
#define	GPIO_IOSEL2		0xB8800912
#define	GPIO_IOSEL3		0xB8800914
#define	GPIO_IOSEL4		0xB8800916
#define	GPIO_DATA1		0xB8800920
#define	GPIO_DATA2		0xB8800922
#define	GPIO_DATA3		0xB8800924
#define	GPIO_DATA4		0xB8800926

#define	BCFGR3			0xB880081C

#define	MSA0			0xB8801000
#define	MSA1			0xB8801004
#define	MSA2			0xB8801008
#define	MSA3			0xB880100C
#define	MSB0			0xB8801010
#define	MSB1			0xB8801014
#define	MSB2			0xB8801018
#define	MSB3			0xB880101C
#define	MBC0			0xB8801020
#define	MBC1			0xB8801024
#define	MBC2			0xB8801028
#define	MBC3			0xB880102C
#define	MBBC0			0xB8801040
#define	MBBC1			0xB8801044
#define	MBBC2			0xB8801048
#define	MBBC3			0xB880104C
#define	MCCR0			0xB8801050
#define	MCCR1			0xB8801054
#define	MCCR2			0xB8801058
#define	MCCR3			0xB880105C
#define	MICR			0xB8801060
#define	MICCR			0xB8801064
#define	MOCR0			0xB8801070
#define	MOCR1			0xB8801074
#define	MOCR2			0xB8801078
#define	MOCR3			0xB880107C

#define	ETHER_BASE0		0xB8802000
#define	ETHER_BASE1		0xB8802400

#define	GETHER_BASE0		0xB8804000
#define	GETHER_BASE1		0xB8805000

#define	FPGA_CNT		0xB881000C

// Ethernet register offset
#define	MACC1			0x0000
#define	MACC2			0x0004
#define	IPGT			0x0008
#define	IPGR			0x000C
#define	CLRT			0x0010
#define	LMAX			0x0014
#define	LSA2			0x0054
#define	LSA1			0x0058
#define	PTVR			0x005C
#define	VLTP			0x0064
#define	MIIC			0x0080
#define	MCMD			0x0094
#define	MADR			0x0098
#define	MWTD			0x009C
#define	MRDD			0x00A0
#define	MIND			0x00A4
#define	AFR			0x00C8
#define	HT1			0x00CC
#define	HT2			0x00D0
#define	CAR1			0x00DC
#define	CAR2			0x00E0
#define	CAM1			0x0130
#define	CAM2			0x0134

#define	RBYTC			0x0140
#define	RPKTC			0x0144
#define	RFCSC			0x0148
#define	RMCAC			0x014C
#define	RBCAC			0x0150
#define	RXCFC			0x0154
#define	RXPFC			0x0158
#define	RXUOC			0x015C
#define	RXLNC			0x0160
#define	RFLRC			0x0164

#define	RCDEC			0x0168
#define	RFCRC			0x017C
#define	RUNDC			0x0170
#define	ROVRC			0x0174
#define	RFRGC			0x0178
#define	RJBRC			0x017C
#define	R64C			0x0180
#define	R127C			0x0184
#define	R255C			0x0188
#define	R511C			0x018C
#define	R1KC			0x0190
#define	RMAXC			0x0194
#define	RVBTC			0x0198

#define	TBYTC			0x01C0
#define	TPKTC			0x01C4
#define	TFCSC			0x01C8
#define	TMCAC			0x01CC
#define	TBCAC			0x01D0
#define	TUCAC			0x01D4
#define	TXPFC			0x01D8
#define	TDFRC			0x01DC
#define	TXDFC			0x01E0
#define	TSCLC			0x01E4
#define	TMCLC			0x01E8
#define	TLCLC			0x01EC
#define	TXCLC			0x01F0
#define	TNCLC			0x01F4
#define	TCSEC			0x01F8
#define	TIMEC			0x01FC

#define	XMT_CFGR		0x0200
#define	XMT_DPR			0x0214

#define	RCV_CFGR		0x0218
#define	RCV_DPR			0x022C
#define	RCV_PDR			0x0230
#define RCV_PDR1		0x0230

#define	XMT_CTLR		0x0204
#define	XMT_DR			0x0208
#define	XMT_STR			0x020C
#define	XMT_APR			0x0210

#define	RCV_CTLR		0x021C
#define	RCV_DR			0x0220
#define	RCV_STR			0x0224
#define	RCV_APR			0x0228
#define	FMSMON			0x025C
#define	CCR			0x0234
#define	ISR			0x0238
#define	MSR			0x023C
#define	DMA_RST			0x0250
#define	RCV_MAC_RST		0x0254
#define	XMT_MAC_RST		0x0258

// Gbit Ethernet register offset
#define	GMACC1			0x0000
#define	GMACC2			0x0008
#define	GIPGIFG			0x0010
#define	GIPGR			0x0018
#define	GLMAX			0x0020

#define	GMIIC			0x0040
#define	GMCMD			0x0048
#define	GMADR			0x0050
#define	GMWTD			0x0058
#define	GMSTA			0x0060
#define	GMIND			0x0068
#define	GPHYC			0x0070

#define	GLSA1			0x0080
#define	GLSA2			0x0088

#define	GCAR1			0x00E0
#define	GCAR2			0x00E8
#define	GCAM1			0x00F0
#define	GCAM2			0x00F8
#define	GSTLC			0x0100
#define	GAFR			0x0108
#define	GHT1			0x0110
#define	GHT2			0x0118
#define	GCFPT			0x0120
#define	GICFPT			0x0128
#define	GMACC3			0x0130
#define	GTIMR			0x0138
#define	GRIMR			0x0140
#define	GTSVREG			0x0148
#define	GRSVREG			0x0150
#define	GFSVREG			0x0158
#define	GRFIC1			0x0180
#define	GRFIC2			0x0188
#define	GRFIC3			0x0190
#define	GTFIC1			0x0198
#define	GTFIC2			0x01A0
#define	GUFCR			0x01A8

#define	GSTIR			0x07D8
#define	GMISCR			0x07E0
#define	GVERID			0x07F0
#define	GPOWD			0x07F8

#define	GR64			0x0400
#define	GR127			0x0408
#define	GR255			0x0410
#define	GR511			0x0418
#define	GR1K			0x0420
#define	GRMAX			0x0428
#define	GRMGV			0x0430
#define	GRBYT			0x0438
#define	GRPKT			0x0440
#define	GRFCS			0x0448
#define	GRMCA			0x0450
#define	GRBCA			0x0458
#define	GRXCF			0x0460
#define	GRXPF			0x0468
#define	GRXUO			0x0470
#define	GRXLN			0x0478
#define	GRFLR			0x0480
#define	GRCDE			0x0488
#define	GRCSE			0x0490
#define	GRUND			0x0498
#define	GROVR			0x04A0
#define	GRFRG			0x04A8
#define	GRJBR			0x04B0

#define	GT64			0x0500
#define	GT127			0x0508
#define	GT255			0x0510
#define	GT511			0x0518
#define	GT1K			0x0520
#define	GTMAX			0x0528
#define	GTMGV			0x0530
#define	GTBYT			0x0538
#define	GTPKT			0x0540
#define	GTMCA			0x0548
#define	GTBCA			0x0550
#define	GTXPF			0x0558
#define	GTDFR			0x0560
#define	GTEDF			0x0568
#define	GTSCL			0x0570
#define	GTMCL			0x0578
#define	GTLCL			0x0580
#define	GTXCL			0x0588
#define	GTNCL			0x0590
#define	GTDRP			0x05A0
#define	GTJBR			0x05A8
#define	GTFCS			0x05B0
#define	GTXCF			0x05B8
#define	GTOVR			0x05C0
#define	GTUND			0x05C8
#define	GTFRG			0x05D0

#define	GRDRP			0x0600
#define	GTFPE			0x0608

#define	GTX_CFGR		0x0800
#define	GTX_DPR	 		0x0808
#define	GTX_DESCMON		0x0810
#define	GTX_STSMON		0x0818
#define	GTX_MBTSZ		0x0820
#define	GTX_SRST		0x0828
#define	GTX_ISR			0x0830
#define	GTX_MSR			0x0838
#define	GTX_PERR		0x0840
#define	GTX_MPERR		0x0848
#define	GTX_ENMON		0x0850

#define	GRX_CFGR		0x0880
#define	GRX_DPR			0x0888
#define	GRX_PDR			0x0890
#define	GRX_PLALM		0x0898
#define	GRX_DESCMON		0x08A0
#define	GRX_STSMON		0x08A8
#define	GRX_MBTSZ		0x08B0
#define	GRX_SRST		0x08B8
#define	GRX_ISR			0x08C0
#define	GRX_MSR			0x08C8
#define	GRX_PERR		0x08D0
#define	GRX_MPERR		0x08D8
#define	GRX_ENMON		0x08E0
#define	GRMII_SPD		0x08E8

#define	GDMATIM			0x0900
#define	GPFTIM			0x0908
#define	GSLV_PERR		0x0910
#define	GSLV_MPERR		0x0918
#define	GIODRSTR		0x0920

// Timer Register Offset
#define	PRE_A			0xB8800A00
#define	PRE_B			0xB8800A02
#define	PRE_C			0xB8800A04
#define	PRE_D			0xB8800A06
#define	PRE_E			0xB8800A08
#define	PRE_F			0xB8800A0A
#define	PRE_G			0xB8800A0C
#define	CLK_SEL_A		0xB8800A10
#define	CLK_SEL_B		0xB8800A12
#define	CLK_SEL_C		0xB8800A14
#define	TC0_STS			0xB8800A20
#define	TC0_EN			0xB8800A22
#define	TC0_DATA0		0xB8800A28
#define	TC1_STS			0xB8800A30
#define	TC1_EN			0xB8800A32
#define	TC1_DATA0		0xB8800A38
#define	TC1_DATA1		0xB8800A3A
#define	TC2_STS			0xB8800A40
#define	TC2_EN			0xB8800A42
#define	TC2_DATA0		0xB8800A48
#define	TC3_STS			0xB8800A50
#define	TC3_EN			0xB8800A52
#define	TC3_DATA0		0xB8800A58
#define	TC4_STS			0xB8800A60
#define	TC4_EN			0xB8800A62
#define	TC4_DATA0		0xB8800A68
#define	TC4_DATA1		0xB8800A6A
#define	TC5_STS			0xB8800A70
#define	TC5_EN			0xB8800A72
#define	TC5_DATA0		0xB8800A78
#define	TC6_STS			0xB8800A80
#define	TC6_EN			0xB8800A82
#define	TC6_DATA0		0xB8800A88
#define	TC7_STS			0xB8800A90
#define	TC7_EN			0xB8800A92
#define	TC7_DATA0		0xB8800A98
#define	TC8_STS			0xB8800AA0
#define	TC8_EN			0xB8800AA2
#define	TC8_DATA0		0xB8800AA8
#define	TC8_DATA1		0xB8800AAA
#define	TC8_DATA2		0xB8800AAC
#define	TC8_DATA3		0xB8800AAE

#define __UX1200E_H__
#endif